This application incorporates by reference Taiwanese application Ser. No. 89106479, filed on Apr. 7, 2000.
1. Field of the Invention
The invention relates in general to a method and system for buffer management, and more particularly to a management method and system for ring buffer and multiple buffer for accelerated graphic port (AGP) interface.
2. Description of the Related Art
Referring to FIG. 1, it illustrates the partial structure of a conventional computer system in block diagram form. A central process unit (CPU) 102 reads data from or writes data into a memory 106 through a chipset 104, such as a north bridge, and the chipset 104 is coupled to a multimedia chip 110 through a bus 108 such as an AGP bus or a peripheral component interface (PCI) bus, wherein the multimedia chipset 110 is employed to process audio, video, and graphic data.
In the computer system, the CPU 102 communicates with the multimedia chip 110 via the chip set 104. Since the multimedia chip 110 have to handle and execute a large amount of computation, when the CPU 102 sends a command signal to the multimedia chip 110, it takes a certain time for the CPU 110 to wait for a command signal being executed by the multimedia chip 110. Thus, it will degrade the performance of the CPU 102. In this way, an AGP buffer is employed to reduce this degradation.
AGP buffer 112 is a storage area in the memory 106, which is used to store AGP command data_associated with multimedia commands to be sent by the CPU 102 to the multimedia chip 110. Firstly, the CPU 102 writes AGP command data into the AGP buffer 112. Next, the multimedia chip 110 reads the AGP command data from the AGP buffer 112 and executes the AGP command data. In addition, the AGP buffer 112 can be modified by the chipset. Further, at a certain time, the AGP buffer 112 can be only read or written. During writing, the CPU 102 should avoid from writing data into a portion in the AGP buffer 112 that has not been read; and during reading, the multimedia chip 110 should avoid reading from a portion in the AGP buffer 112 into which data has not been written.
Referring to FIGS. 2A-2D, they illustrate a partial structure of another conventional computer system using integrated chipset 202, 206, 208, and 210 respectively.
In FIG. 2A, the CPU 102 accesses the memory 106 through the integrated chipset 202. The integrated chipset 202 includes the chipset 104 and multimedia chip 110, where between the chipset 104 and the multimedia chip 110, there is an internal interface 204, such as an AGP like interface or a peripheral component interconnect (PCI) like interface.
In FIG. 2B, the integrated chipset 206 includes the CPU 102 and chipset 104. In addition, the CPU 102 accesses the memory 106 by using the chipset 104 via the bus 108.
In FIG. 2C, the integrated chipset 208 includes the CPU 102, chipset 104, and multimedia chip 110. Likewise, the internal interface between the chipset 104 and the multimedia chip can be an AGP like interface or a PCI like interface, for instance.
In FIG. 2D, the integrated chipset 210 includes the CPU 120 and the multimedia chip 110.
Referring now to FIG. 3, it illustrates the relation among software and hardware components in the conventional computer system. Application program (AP) 302 is a program directly communicating with a user. Operating system (OS) 304 includes application program interface (API) 306 and driver interface 308. In addition, a device driver 312 controls the multimedia chip 110. The API 306, defined by the OS 304, is the interface between the OS 304 and AP 302 for support function calls by the AP 304. The driver interface 308, defined by the OS 304, is the interface between the OS 304 and the device driver 312. Besides, the device driver 308 programs the multimedia chip 110 so as to manage the AGP buffer 112. To be specific, programming the multimedia chip 110 is to read and write to registers (not shown) associated with the multimedia chip 110, where the registers can be designed as ones inside the multimedia chip 110 or chipset 104.
Referring to FIG. 4, it illustrates a first conventional approach with an AGP buffer. Beginning register 402 is to store the beginning address of the AGP buffer 112 while ending register 406 is to store the ending address of the AGP buffer 112. Alternatively, the length of the AGP buffer 112 can be stored in the ending register 406, leading to the same effect. For this example, the ending register 406 is to store the ending address of the AGP buffer 112.
The device driver 312 controls the multimedia commands to be sent by the CPU 102 to the multimedia chip 110. First, the AGP command data associated with the multimedia commands are written into the AGP buffer 112. Then, the multimedia chip 10 reads and executes the AGP command data in the AGP buffer 112.
Referring to FIG. 5, it illustrates a method for managing the AGP buffer shown in FIG. 4. First, the method begins in step 502, where the device driver 312 writes the AGP command data into the AGP buffer 112. Then, the method proceeds to step 504. In step 504, the device driver 312 sets the beginning register 402 and the ending register 406. That is, the beginning and ending addresses of the AGP buffer 112 are written into the beginning register 402 and the ending register 406, respectively. Next, step 506 is performed, where the device driver 312 triggers the multimedia chip 110 to start reading the AGP command data in the AGP buffer 112. Then, the method proceeds to step 508. In step 508, it is determined whether the device driver 312 has AGP command data left to be written into the AGP buffer 112. If yes, step 510 is performed; otherwise, the method ends.
In step 510, a determination is made whether the multimedia chip 110 is idle. That is to determine whether the multimedia chip 110 stops accessing the AGP buffer 112 and stays idle. If yes, step 502 is repeated, where the device driver 312 writes AGP command data into the AGP buffer 112. If not, step 510 is repeated. In this way, the device driver 312 can continue to write AGP command data into the AGP buffer 112 only if the multimedia chip 110 is idle.
In the method above, step 502 and step 504 are interchangeable. In addition, in each iteration from steps 502 to 510, the AGP buffer 112 can correspond to different area in the memory 106.
However, the method has a disadvantage of inefficiency. Since the method does not use read pointer to indicate the address that the multimedia chip 110 uses during performing reading on the AGP buffer 112, the device driver 312 must be waiting to perform reading until the multimedia chip 100 is idle, resulting in a waste of time. Besides, this makes the CPU 102 cannot execute other application and the multimedia chip 110 resumes operating after a waiting time. Moreover, in order to prevent the multimedia chip 110 from reading the portion of the AGP buffer 112 having not been written into, the device driver 312 triggers the multimedia chip 110 only after completing read operations on the AGP buffer 112. In this way, the multimedia chip 110 can perform reading on the AGP buffer 112.
Referring to FIG. 6, it illustrates another conventional AGP buffer. A first beginning register 602 and a first ending register 604 are used for storing the beginning and ending addresses of a first AGP buffer 606 respectively. A second beginning register 608 and a second ending register 610 are used for storing the beginning and ending addresses of a second AGP buffer 612 respectively. In addition, the AGP buffer 112 includes the first AGP buffer 606 and second AGP buffer 612.
FIG. 7 shows a method for managing AGP buffers in FIG. 6 in a flow chart. The method begins and proceeds to step 702. In step 702, the device driver 312 writes AGP command data into the first buffer 606, and the method then proceeds to step 704. In step 704, the device driver 312 is to determine whether the multimedia chip 110 is idle, that is, determining whether the multimedia chip reads AGP command data from the AGP buffer 112. If yes, step 706 is performed; otherwise, the method repeats from step 704.
In step 706, the device driver 312 writes the beginning and ending addresses of the first AGP buffer 606 into the first beginning register 602 and a first ending register 604 respectively. Then, step 708 is performed. In step 708, the device driver 312 triggers the multimedia chip 110 to read AGP command data from the first AGP buffer 606, and the method then proceeds to step 710. In step 710, the device driver 312 writes the AGP command data into the second AGP buffer 612. Then, in step 712, the device driver 312 is to determine whether the multimedia chip 110 is idle, that is, to determine whether the multimedia chip 110 is not reading AGP command data from the AGP buffer 112. If it is idle, the method proceeds to step 714; otherwise, repeating step 712.
In step 714, the device driver 312 writes the beginning and ending addresses of the second AGP buffer 612 into the second beginning register 608 and second ending register 610 respectively. Then, step 716 is executed. In step 716, the device driver 312 triggers the multimedia chip 110 to read AGP command data from the second AGP buffer 612. The method then proceeds to step 718. In step 718, the device driver 312 is to determine whether there are any AGP command data to be written into the AGP buffer 112. If yes, the method repeats from step 702; otherwise, the method ends.
In terms of performance, the method shown in FIG. 7 is better than the method shown in FIG. 5. However, the former still has disadvantages. For example in step 704 or 712, the method proceeds to the next step when the multimedia chip 110 is idle, resulting in an additional waiting time. Besides, in the method shown in FIG. 7, all AGP command data must first fill in either the AGP buffer 606 or 612. When one of the two buffers is filled with AGP command data, the following AGP command data are allowed to be filled into the other buffer. In this way, the multimedia chip 110 must wait to perform reading of the AGP command data until one of the AGP buffers 606 and 612 is filled. Thus, it delays the multimedia chip 110 reading AGP command data, resulting in a reduction in system performance.
It is therefore an object of the invention to provide a method and system for buffer management. By the invention, the multimedia chip can read an AGP buffer with the least delay and without waiting for one or more AGP buffers to be filled completely. In this way, usage efficiency of the AGP buffers are increased, and the time spent waiting for the idle multimedia chip is reduced. Besides, the CPU can use the portion that the multimedia chip has read for storing new command data.
The invention achieves the above-identified object by providing a system for buffer management. The system includes a central processing unit, a multimedia chip, a buffer, a beginning register, an ending register, and a pause storage unit. The central processing unit (CPU) is to access a memory through a chipset, and the multimedia chip is coupled to the chipset via a bus. The buffer is used for storing a plurality of command data associated with a plurality of multimedia commands that the CPU is to send to the multimedia chip, wherein the multimedia chip reads the command data from the buffer and executes the command data. The beginning register is employed to store a beginning address of the buffer, and the ending register is used to store an ending address of the buffer or a buffer length. In addition, content of the pause storage unit includes a data address associated with the command data.
The invention achieves the above-identified object by providing a method for buffer management, for managing write operation for a first device to write pieces of data into a buffer, and read operation for a second device to read the pieces of the data from the buffer. The buffer has a beginning address, an ending address, a buffer length indicative of the size of the buffer. The method includes a write process and a read process, and uses a beginning register, an ending register, a pause storage unit, and a read pointer, wherein the read pointer is to point to an address of data being read from the buffer during the read operation. The write process includes the following steps. (a) Write a first piece of the data into the buffer, wherein the first piece of the data written into the buffer is associated with a first data address in the buffer. (b) Write the first data address into the pause storage unit. (c) Trigger the second device. (d) Repeat steps (a) to (d) when there are data left to be written into the buffer. In addition, before step (c) the write process further includes the step of (e) writing the beginning address into the beginning register, and writing the ending address or the buffer length into the ending register. On the other hand, the read process includes the following steps. (a1) Set the read pointer pointing to the first data address in the buffer. (b1) Read data of an address pointed to by the read pointer when the second device is triggered. (c1) Continuously read data next to the data of the address pointed to by the read pointer when the address pointed to by the read pointer is different from content of the pause storage unit, and read content of the beginning register when the address pointed to by the read pointer is identical to content of the ending register until all of the data are read.